Welcome to DaveO's home page:
Don't you wish that people couldn't include pictures of
themselves?
In November 1999, I was working part-time for a small networking
technology company called Layer 5 and working full time at Stanford as
a research associate. Well, things happened like they seem to in the
valley, and Layer 5 was bought by Juniper Networks. As of January
1st, I left the sheltered life of the academic world for the harsh
reality of industry, and I am now a full-time employee of Juniper.
A bit of FLASH history:
Around March 1st, 1998, FLASH booted multiprocessor IRIX on a 2
processor system, and can now be officially considered a
multiprocessor. Woohoo!
The machine is now rock solid at four processors, and we think we've
found all the bugs we are going to find given the workarounds we are
running with (note: this is very different than saying we've found all
the bugs... :). Early in 1999, we should have a 32-65P FLASH machine
up and running. The actual processor count will depend on how much
money we have and how good of a deal we can get for the various
pieces.
8 April 1999: we taped out MAGIC 2.0. This version of the chip should
have all of our logic bugs and our major timing bug fixed. The result
should be a MAGIC that can run at 80+Mhz. We should be getting these
chips back mid-summer.
We have the hardware to build 72 FLASH nodes. These will be
configured into a64P and a set of smaller machines. The only things
holding us up at the moment are a lack of MAGIC chips and the SRAMS
that make up the MAGIC data cache.
1 June 1999: We received 16 more MAGIC 1.0 parts. Now we have all the
pieces necessary to build a larger FLASH machine. Once we find out if
the new MAGICs are actually tested, we'll send them, the SRAMS, and
the revC PCBs to Celestica.
16 May 2000: Long time- no updates. The MAGIC 2.0 parts came back and
run happily at 75Mhz. We now have 70ish FLASH nodes configured as
various machine sizes, the largest is currently 16 processors. Each
node has a 225Mhz R10000 with 2MB of cache, a 75MHz MAGIC part, 256MB
of SDRAM, and a port into an SGI MetaRouter.
25 May 2000: Big milestone... Joel just booted IRIX6.4 on a 32
processor machine!!! Unbelievable!
My folks have gone digital and embraced the web. You can find them
here.
Of course, if they start
putting up embarasing baby pictures, or write up god-awful childhood
occurances, this link will disappear faster than you can say 'Bad Son'.
You can check out my vanity web domain here.
If you are interested in what I've worked on, check out my publications:
- D. Ofelt, J.L. Hennessy, "Efficient Perforamance Prediction for
Modern Microprocessors" in To Appear in ACM SIGMETRICS
International Conference on Measurement and Modeling of Computer
Systems, pp ??-??, June 2000 (PDF)
- D. Ofelt, "Efficient Performance Prediction for Modern
Microprocessors", Stanford University Thesis, August 1999.
(PDF)
- K. Olukotun, M. Heinrich, and D. Ofelt, "Digital System
Simulation: Methodologies and Examples" DAC '98
- M. Heinrich, D. Ofelt, M. Horowitz, and J. Hennessy, "Hardware/Software Codesign of the Stanford FLASH Multiprocessor" in Proceedings of the IEEE Special Issue on Hardware/Software Co-design, Vol. 85, No. 3, March 1997 (Postscript)
- M. Martonosi, D. Ofelt, and M. Heinrich, "Integrating Performance Monitoring and Communication in Parallel Computers" in ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 138-147, May 1996 (Postscript)
- M. Heinrich, J. Kuskin, D. Ofelt, et al., "The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor" in Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 274-285, 1994 (Postscript)
- J. Kuskin, D. Ofelt, M. Heinrich, et al., "The
Stanford FLASH Multiprocessor" in Proceedings of the 21st International Symposium on Computer Architecture (ISCA), pages 302-313, April 1994 (Postscript)
And then there is the paper that I can't even explain what the title
means any more...
-
Negative Poisson's Ratio in Percolating Elastic Network, D. Ofelt, J.G.
Zabolitzky, and D.J. Bergman, University of Minnesota Supercomputer
Institute Research Report UMSI 87/2, January 1987.
If you need to get ahold of me, there are several options. I am
usually in CA, but I like to travel...
Schedule:
M -F : At Juniper
Sa-Su: At Home
Travel Plans:
* None :(
Home
------------------------
407 Santa Clara
Redwood City, CA 94061
(650) 369-7284 Home
(650) 544-8401 Cell <--- NEW
Office - Juniper Networks
-------------------------
380 Bernardo Ave
Mountain View, CA 94043
Tel: (650) 318-3245
