Tools Page

Here's some info on a verilog tool I've been developing

vex/ivex

Features:

  • netlist browsing
  • general renaming
  • fix synopsys spewage
  • get rid of \xyz[123] crap
  • rename n283 to more useful names sometimes (i.e. inv_Stall)
  • busmerging (potentially useful during debugging)
  • remove gratoutis(sp?) trans, assign statements
  • clock splitting
  • instance renaming
  • basic lint
  • tristate bus checking
  • identify all tristate buses
  • check for multiple drivers during reset/scan
  • Scan
  • partial insertion (usually stuff mentor couldn't handle)
  • scan chain traversal
  • clocktree stuff (for motive clock skew analysis)
  • pdef file generation
  • lsi/dppl command file generation
  • basic logic simulation
  • gate eate (in progress)
  • partial evaluator (in progress)
  • ATPG support
  • SDF support
  • partswap (+ fixhd - fixes some synopsys braindamage)
  • in progress:
  • improved handling of behavioral verilog
  • ...

    • gvex

  • graphical netlist display
  • atpg info (todo: get a screenshot)
  • ...gengraph... talk about it
  • source browser (like interview c++ class browser) (screenshot)
  • in progress:
  • browser improvements
  • segv - state enumeration graph viewer (screenshot) (todo: link to what description of whats in the screenshot)
  • ...

    • bdd package

  • perl interface to generic bdd package
  • generate bdds from verilog parse tree
  • command line expression parser
  • limited state enumeration
  • in progress:
  • very new - heavy hacking in progress
  • ...

    • Misc tools

    Requirements

  • perl (version 5)
  • verilog parser - from berkely + homegrown
  • perl/tk
  • dot - AT&T graphing tools (very nice)
  • bdd package - from the Formal Verification Group at Eindhoven University of Technology

    • Limitations

  • setup - is currently slightly complicated and hacked for the local computing environment.
  • recognized verilog - although the parser itself is relatively general, parts of the tool are targeted to a synthesizable subset of verilog that we use here. Fruthermore, parts of the tool are not guarenteed to be complete: a commonly used, perfectly legal, synthesizable piece of verilog might cause the tool to barf, although I will be happy to fix these cases.
  • feature set - the feature set is evolving: new features are probably buggy, old features might not have been recently used & tested, and might be broken.
  • memory requirements - the tool is a memory hog.
  • synthesis library/environment - although an attempt has been made to isolate synthesis library data into a configuration file (which unfortunately isn't compatible with any standards), some knowledge of the synthesis library is still hacked into the code in various places.

    • Download

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