What's New?

(entries for this year only)

New pages in the architecture section will certainly show up here as they are added, and we'll also keep track of additions in the operating system section, the applications section, and the non-SUIF portion of the compilers and languages section. For new additions to the SUIF site, you'll need to go there and check it out for yourself.

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03/11/98
...and even more, this time featuring our three-node setup.
03/03/98
More FLASH pictures!
02/20/98
Forging ahead, we have a two-node FLASH system working here: 
IRIX (foobar)

login: root
Password:
IRIX Release 6.4-yhuang-buildtree6.4-FLASH IP27 foobar
Copyright 1987-1997 Silicon Graphics, Inc. All Rights Reserved.
Last login: Fri Feb 20 19:30:21 PST 1998 by UNKNOWN@havoc.Stanford.EDU
foobar 1# hinv
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Processor 1: 176 MHZ IP27 
Processor 0: 174 MHZ IP27 
Main memory size: 112 Mbytes
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 1 Mbyte
IOC3 serial port: tty1
IOC3 serial port: tty2
Integral Fast Ethernet: ef0, version 0
foobar 2#
I have tracked down the digital camera again and will hopefully have some more pictures soon.
10/21/97
The MAGIC chip is so far working like a charm. We're proud of our baby, so we have some pictures to show you.
10/15/97
BRINGUP HAS BEGUN (woo hoo!)
8/4/97
Latest schedule: MAGIC prototypes due back in our hands on September 20.
1/21/97
Added Heinlein et al's paper Coherent Block Data Transfer in the FLASH Multiprocessor (IPPS 1997) to the FLASH Architecture papers.
[logo] FLASH
Last modified 03/11/98 by Joel Baxter, webmaster@www-flash.stanford.edu.