FLASH Architecture

The FLASH (Flexible Architecture for SHared memory) multiprocessor will be a scalable multiprocessor able to support a variety of communication models, including shared memory and message passing protocols, through the use of a programmable node controller. We plan to provide the architectural support necessary to use FLASH as a traditional "standalone" supercomputer, a compute server, a robust multiuser system, or a distributed system.

The key to our design is the node controller, MAGIC (Memory And General Interconnect Controller), shown in relation to the system in the diagram above. MAGIC is a custom chip centered around the Protocol Processor, a programmable protocol engine based on the TORCH processor design. The above figure is a clickable imagemap that is the entrance point for a hierarchical tour of the FLASH system, accompanied by images and excerpts from FLASH documents. This is a work in progress; currently you can only click on MAGIC or the the microprocessor.

We are developing the FLASH system in partnership with the Information Technology Office in ARPA. We are also indebted to the cooperation of MIPS Technologies, whose R10000 processor will be the compute processor for the FLASH prototype.

This site contains the following FLASH architecture resources:

A list of personnel
Publications:
- By FLASH team members
- Other (DASH,etc.)
A general status report
Slides from FLASH team presentations

FLASH

Last modified 7/9/96 by Joel Baxter, webmaster@www-flash.stanford.edu.